1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
2. Background Art
Conventionally, a semiconductor device is manufactured, for example, through the following process. A tunnel insulating film, a polysilicon layer doped with impurities for a floating gate electrode, a stopper film for CMP (Chemical Mechanical Polishing), and a mask film for RIE (Reactive Ion Etching) are sequentially deposited on the surface of a semiconductor substrate, which is doped with desired impurities.
The mask film, the stopper film, the polysilicon layer, and the tunnel insulating film are sequentially etched by RIE. Furthermore, an exposed region of the semiconductor substrate is etched to form an isolation trench.
A silicon oxide film is formed on the exposed surface of the semiconductor substrate by thermal oxidation, and another silicon oxide film is further deposited on the entire surface, to completely bury the silicon oxide film in the isolation trench. The silicon oxide film and the mask film are removed by CMP to planarize the surface, to make the surface of the stopper film be exposed.
After selectively removing the stopper film by etching, the exposed surface of the silicon oxide film is etched using a diluted hydrofluoric acid solution, to make the sidewall surfaces of the polysilicon layer be exposed.
After an inter electrode insulating film with a three-layer structure including a silicon oxide film, a silicon nitride film, and a silicon oxide film is deposited on the entire surface, a conductive layer with a two-layer structure including a polysilicon layer and a tungsten silicide layer is deposited, and a mask film for RIE is then deposited. The conductive layer is to be etched to form a control gate electrode. In this specification, layers in each multi-layer structure are described in order from the lowest layer to the highest layer.
The mask film, the conductive layer, the inter electrode insulating film, and the polysilicon layer are sequentially etched by RIE, to form a slit part between stacked cells, the slit part extending in a direction perpendicular to the isolation trench. Thereby, the shapes of the floating gate electrode and the control gate electrode are determined.
After forming a silicon oxide film on the exposed surface by thermal oxidation as an electrode sidewall oxide film, a cell diffusion layer is formed, and a silicon oxide film is then formed as an inter layer dielectric so as to cover the entire surface. Subsequently, an interconnect layer and the like are formed to complete nonvolatile memory cells. However, this manufacturing method has the following problems.    (a) As nonvolatile memory cells become finer, the reliability of the memory cells will be significantly lowered due to the cell width (channel width) in the word-line direction (channel-width direction) becoming smaller. Accordingly, if oxidation performed for mending RIE process damage before filling the isolation trenches with the silicon oxide film is performed by isotropic oxidation such as thermal oxidation, the cell width becomes excessively small, lowering the reliability of the memory cells. Concurrently, the dopant concentration is lowered due to the dopant in the channel regions being drawn into the oxide film as a result of thermal oxidation of the sidewalls of the semiconductor substrate, causing erroneous writing in the memory cells.
Also, where the memory cells become finer, resulting in a decrease in the isolation trench width, if the isolation trenches are substantially completely filled with an insulating film, parasitic capacitances between adjacent elements cannot be ignored because they may cause erroneous memory operation, which is what is called “inter-cell interference”. Accordingly, it is necessary to provide cavities in the isolation trenches. However, in case that an insulating film is provided into the isolation trenches by means of deposition, it is difficult to form cavities having the same shape because of difficulty in depositing the insulating film on the sidewall parts of the isolation trenches.    (b) In nonvolatile memory cells, when a polysilicon layer is processed by RIE to form floating gate electrodes, the lower end parts of the floating gate electrodes are formed in a pointed shape, locally generating a high electric field during writing/erasing operation for the memory cells, resulting in lowering the reliability of the memory cells. Therefore, the locally-generated high electric field is reduced by forming a silicon oxide film, which is an electrode sidewall oxide film, by thermal oxidation to increase the distance between the lower end part of each floating gate electrode and the semiconductor substrate surface and also increase the curvature of the lower end parts of the floating gate electrodes. However, as the memory cells become finer, the oxidation amount in the sidewall parts of the floating gate electrodes, which are formed by thermal oxidation, cannot be ignored and the cell width (channel length) in the bit-line direction (channel-length direction) becomes excessively small, making the control of the memory cell characteristics difficult, causing erroneous memory operation.
Furthermore, as the memory cells become finer, when a polysilicon layer is processed by RIE to form floating gate electrodes, there is a tendency that the width of the floating gate electrodes becomes wider toward their lower parts (i.e., has what is called a skirt shape). Accordingly, the lower end parts of the floating gate electrodes are formed in a sharply pointed shape, which is a factor promoting the lowering of the cell reliability.    (c) Transistor elements also have a problem similar to problem (b), which is a factor of lowering the transistor reliability.    (d) In nonvolatile memory cells, when the control gate electrodes are formed by a metal, a metal silicide or a metal nitride such as tungsten silicide, nickel silicide, cobalt silicide, tungsten, tantalum, titanium, tungsten nitride, tantalum nitride or titanium nitride, the following problems are caused. A mask film, a conductive layer, an inter electrode insulating film and a polysilicon layer are sequentially processed by RIE to form slit parts between the stacked cells, thereby determining the shapes of the floating gate electrodes and the control gate electrodes. When a silicon oxide film, which is called an electrode sidewall oxide film, is formed on the exposed surface by thermal oxidation, oxidation of the metal, the metal silicide or the metal nitride are accelerated, causing a problem in a decrease in conductivity of the control gate electrodes. Also, expansion caused by oxidation has adverse effects on the subsequent diffusion layer formation process by ion implantation.    (e) Also, transistor elements using a metal, a metal silicide or a metal nitride for gate electrodes have a problem similar to that of the nonvolatile memory cells described in (d) above.    (f) In nonvolatile memory cells, where the inter electrode insulating film is formed of a high-permittivity metal oxide film containing oxygen, such as alumina, hafnia, zirconia, aluminum silicate, hafnium silicate or zirconium silicate instead of the three-layer structure consisting of a silicon oxide film, a silicon nitride film and a silicon oxide film, the following problem is caused. When, in the process of forming a silicon oxide film, which is called an electrode sidewall oxide film, on the exposed surface by thermal oxidation after sequentially processing the mask film, the conductive layer, the inter electrode insulating film and the polysilicon layer by RIE to form slit parts between the stacked cells, thereby determining the shapes of the floating gate electrodes and the control gate electrodes, the thermal oxidation is performed in an atmosphere including a reducing gas such as a hydrogen gas, a reaction to abstract oxygen from the inter electrode insulating film occurs, causing deterioration in the insulation property of the inter electrode insulating film.    (g) In some nonvolatile memories, peripheral transistors are formed on a planar part of a semiconductor substrate and memory cells are formed on a partial SOI (Silicon on Insulator) substrate of the same semiconductor substrate. In such a case, a step part is formed at the boundary between the planar part and the partial SOI substrate by etching. Conventionally, both the planar part and a sidewall providing the step part are then oxidized by thermal oxidation.
Subsequently, even though the sidewall oxide film is removed by etching, the position of the step part is displaced as a result of oxidation and etching. This position corresponds to the boundary between the peripheral transistors and the memory cells, and is used as a reference for pattern formation. Consequently, displacement of this position causes pattern displacement.
A conventional nonvolatile memory cell manufacturing method is disclosed in, for example, JP-A 2006-222203 (KOKAI).